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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片 |
| 文件頁數(shù)： | 46/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
46
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.10 P
HYSICAL
L
AYER
C
ONTROL REGISTER
This register has write access only in Normal and Standby modes; it allows the CAN and the LIN physical layer to be
configured.
Table 11
PLC - Physical Layer Control register (address 11) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
A1, A0
RRS
register address
Read Register Select
11
1
0
1
select Physical Layer Control register
read the General Purpose Feedback register 1 (GPF1)
read the Physical Layer Control Feedback register (PLCF)
read the register selected by RRS without writing to the
Physical Layer Control register
read the register selected by RRS and write to Physical
Layer Control register
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
allows Selective Sleep state to be entered; cleared
whenever the UJA1061 enters On-line or Active mode
no Selective Sleep mode allowed (default)
256 ms time until CAN falls into Off-line (400 ms after
Wake-up)
64 ms time until CAN falls into Off-line (400 ms after
Wake-up)
CAN transmitter is disabled; allows setting ‘listen only’
behaviour; set also due to a detected short at V2 or a
RXDC recessive or TXDC dominant clamping failure
CAN transmitter is enabled
TXD signal is forwarded to RXD during CAN
transmitter OFF
TXD signal is not forwarded to RXD during CAN
transmitter OFF
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
up to 10 kbit/s
up to 20 kbit/s
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
LIN termination supplied out of BAT42
LIN termination is always related to BAT14
12
RO
Read Only
0
11
reserved
0
10
CPNC
CAN Partial
Networking Control
1
0
1
9
COTC
CAN Off-line Time
Control
0
8
CTC
CAN Transmitter
Control
1
(1)
0
7
CRC
CAN Receiver
Control
1
(2)
0
6
reserved
0
5
reserved
0
4
LSC
LIN Slope Control
1
0
0
3
reserved
2
L42C
LIN 42 V Control
1
0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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