參數(shù)資料
型號(hào)： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù)： 69/81頁(yè)
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
69
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
9
T
vj
=
40 to + 150
°
C; V
BAT42
= 5.5 to 52 V; V
BAT14
= 5.5 to 27 V; unless otherwise specified. All voltages are defined
with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction
temperature range by design. Products are 100% tested at 125
°
C ambient temperature on wafer level (pre-testing).
Cased products are 100% tested at 25
°
C ambient temperature (final testing). Both pre-testing and final testing use
correlated test conditions to cover the specified temperature and power supply voltage range.
AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Serial Peripheral Interface (SPI) timing (pins SCS, SCK, SDI, SDO)
(see Fig.19)
T
cyc
t
lead
t
lag
t
SCKH
t
SCKL
t
su
t
h
t
DOV
t
SSH
t
SSL
CAN transceiver (pins CANL, CANH, TXDC and RXDC)
clock cycle time
enable lead time
enable lag time
clock HIGH time
clock LOW time
input data set-up time
input data hold time
output data valid time
SPI select HIGH time
SPI select LOW time
480
240
240
190
190
100
100
200
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock is low when SPI select falls
clock is low when SPI select rises
pin SDO, C
L
= 10 pF
t
t(rec-dom)
output transition time
recessive to dominant
output transition time
dominant to recessive
propagation delay TXDC
to RXDC (HIGH to LOW
transition)
propagation delay TXDC
to RXDC (LOW to HIGH
transition)
bus failure detection time
10 to 90 %; C1 = 10 nF; C2 = 0 nF;
R1 = 100
; see Figs 15 and 16
90 to 10 %; C1 = 1 nF; C2 = 0 nF;
R1 = 100
; see Figs 15 and 16
50 % V
TXDC
to 50 % V
RXDC
;
C1 = 10 nF; C2 = 0 nF; R1 = 100
;
see Figs 15 and 16
50 % V
TXDC
to 50 % V
RXDC
;
C1 = 1 nF; C2 = 0 nF; R1 = 100
;
see Figs 15 and 16
bus failure HxBAT; Active mode,
On-line and Selective Sleep mode;
V
V2
= 5 V
bus failure HxVCC
bus failures LxGND and HxL
bus failure LxBAT; Active mode,
On-line and Selective Sleep mode;
V
V2
= 5 V
continuously dominant clamped
CAN-bus detection time (start after
detecting HxVCC); Active mode,
On-line and Selective Sleep mode;
V
V2
= 5 V
0.6
1.2
μ
s
t
t(dom-rec)
0.3
0.7
μ
s
t
PHL
1.0
1.8
μ
s
t
PLH
1.2
1.9
μ
s
t
BUS(fail)(det)
7
38
μ
s
1.6
0.9
0.3
8.0
1.6
1.6
ms
ms
ms
0.3
1.6
ms
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參數(shù)描述
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UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
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UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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