參數(shù)資料
型號(hào): UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 19/81頁
文件大?。?/td> 323K
代理商: UJA1061
2004 Mar 22
19
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
mce629
set
reset
LOW
event
action
set
reset
HIGH
(pin RSTN = LOW)
< 256 ms
t > t (reset mode)
(1 ms or 20 ms)
pin RSTN = HIGH
NORMAL
Reset mode: 1 ms or 20 ms
START-UP
watchdog init OK
t < 256 ms
set
reset
LOW
set
reset
HIGH
(pin RSTN = LOW)
< 256 ms
t > t (Reset mode)
(here always 20 ms)
pin RSTN = HIGH
(pin RSTN
= LOW)
256 ms
FAIL-SAFE
Reset mode: 20 ms
RESTART
wait
WATCHDOG
init
wait
WATCHDOG
init
t > 256 ms
AND no
undervoltage V1
t > 256 ms
OR undervoltage V1
oscillator
fail
(pin RSTN = HIGH
AND RSTN driven LOW)
> 128 ms
watchdog too early/time-out
OR interrupt ignored
>
256 ms
OR wake-up event
OR V1 active AND V1 undervoltage
OR V1 current monitor
OR (V3 overload AND Sleep mode)
OR wrong mode register code
OR Flash entry enabled
Reset mode: no change
reset threshold: no change
(pin RSTN = LOW)
256 ms
set Reset mode: 20 ms
set reset threshold: HIGH
t
>
256 ms
set Reset mode: 20 ms
set reset threshold: HIGH
watchdog init OK
Power-on
Reset mode: 20 ms
reset threshold: HIGH
RSTN externally
forced falling
edge
Fig.8 Reset state description.
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