參數(shù)資料
型號(hào)： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù)： 41/81頁(yè)
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
41
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.6
I
NTERRUPT
E
NABLE
F
EEDBACK REGISTER
This register allows the current setting of the interrupt enable bits to be read back.
Table 7
IEF - Interrupt Enable Feedback register (address 01) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
12
A1, A0
RRS
RO
register address
Read Register Select
Read Only
01
0
1
read Interrupt Enable Feedback register
read the Interrupt Enable Feedback register without writing
to Interrupt Enable register
read the Interrupt Enable Feedback register and write to
Interrupt Enable (previous content is reflected during read)
a watchdog overflow during Standby mode causes an
interrupt instead of a reset
no interrupt forced
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
exceeding or dropping below the GND shift limit causes an
interrupt
no interrupt forced
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; within Start-up and Restart mode, a
reset is performed instead of an interrupt
no interrupt forced, SPI access simply ignored if wrong
number of cycles is applied (more than, or less than 16)
falling edge at SENSE forces an interrupt
no interrupt forced
detection of a short circuit at V2 or V3 forces an interrupt
no interrupt forced
any change of the CAN failure status forces an interrupt
no interrupt forced
any change of the LIN failure status forces an interrupt
no interrupt forced
a negative edge at WAKE generates an interrupt in
Normal, Flash or Standby modes
a negative edge at WAKE generates a reset in Standby
mode
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
CAN-bus event results in a wake-up interrupt
CAN-bus event results in a reset
LIN-bus event results in a wake-up interrupt
LIN-bus event results in a reset
0
11
WTIE
Watchdog Time-out
Interrupt Enable
1
0
1
10
OTIE
Over-temperature
Interrupt Enable
0
1
9
GSIE
GroundShiftInterrupt
Enable
0
1
8
SPIFIE
SPI clock count
Failure Interrupt
Enable
0
7
BATFIE
BAT Failure Interrupt
Enable
1
0
1
0
1
0
1
0
1
6
V2V3FIE
V2/V3 Failure
Interrupt Enable
5
CANFIE
CAN failure Interrupt
Enable
4
LINFIE
LIN Failure Interrupt
Enable
3
WIE
Wake-up Interrupt
Enable
0
2
reserved
0
1
CANIE
CAN interrupt enable
1
0
1
0
0
LINIE
LIN interrupt enable
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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