參數(shù)資料
型號： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù)： 42/81頁
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
42
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.7
I
NTERRUPT REGISTER
This register allows the cause of an interrupt event to be read. The register is cleared upon read access and upon any
reset event. Hardware makes sure that no interrupt event is lost in case there is a new interrupt forced while reading the
register. The INTN pin is forced HIGH after reading the interrupt register for a defined period of time in order to make
sure that there is always an edge event guaranteed at the INTN pin.
The interrupts can be classified into two classes:
One in which the UJA1061 must react immediately due to timing-sensitive interrupts (SPI Clock CAN failure which
needs an immediate resend of a new SPI command, and BAT failure which needs immediate saving of critical data
into the non-volatile memory)
One which does not need an immediate reaction (OVERTEMP, Ground Shift, CAN and LIN failures, V2 and V3 failures
and the wake-ups via CAN, LIN and WAKE. These interrupts will be signalled in Normal Mode and Flash Mode via the
INTN pin to the microcontroller once per watchdog period (maximum).
Table 8
INT- Interrupt register (address 01) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
12
A1, A0
RRS
RO
register address
Read Register Select
Read Only
01
1
1
read Interrupt register (INT)
read the Interrupt register without writing to Interrupt
Enable register
read the Interrupt register and write to Interrupt Enable
register
a watchdog overflow has occurred during Standby mode
no interrupt
the temperature warning limit has been exceeded or has
dropped below
no interrupt
the GND shift limit has been exceeded or has dropped
below
no interrupt
wrong number of CLK cycles (more than, or less than 16)
during SPI access; within Start-up and Restart modes, a
reset is performed instead of an interrupt
no interrupt; SPI access is ignored if wrong number of
cycles is applied (more than, or less than 16)
falling edge at SENSE forces an interrupt
no interrupt
short-circuit detected at V2 or V3 (details within system
status register 1)
no interrupt
CAN failure status has changed
no interrupt
LIN failure status has changed
no interrupt
a negative edge at WAKE has been detected
no edge
0
11
WTI
Watchdog Time-out
Interrupt
1
0
1
10
OTI
Over-Temperature
Interrupt
0
1
9
GSI
Ground Shift Interrupt
0
1
8
SPIFI
SPI clock count
Failure Interrupt
0
7
BATFI
BAT Failure Interrupt
1
0
1
6
V2V3FI
V2/V3 Failure
Interrupt
0
1
0
1
0
1
0
5
CANFI
CAN Failure Interrupt
4
LINFI
LIN Failure Interrupt
3
WI
Wake-up Interrupt
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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