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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎芯片 |
| 文件頁數(shù)： | 52/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
52
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Table 16
GPF0 - General Purpose Feedback register 0 (address 10) bit description
Note
1.
During power-up, the bits of the General Purpose register 0 (GP0) will be loaded with a ‘Device Identification Code’
consisting of the SBC type and SBC version. Bit 11 of GP0 will reflect a logic 0 indicating the content of this register
to be the ‘Device Identification Code’ after Power-on of the SBC. Once written to this register, bit 11 will be set to a
permanent logic 1 indicating that the device code has been overwritten with application-specific information. Bit 11
cannot be reset any more with software control. Bit 11 will be cleared again with the next Power-on condition at
pin BAT42 with reloading the device code into GP0.
Table 17
GP1 - General Purpose Feedback register 1 (address 11) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
12
A1, A0
RRS
RO
register address
Read Register Select
Read Only
10
1
1
read general purpose feedback register 0 (GPF0)
read the General Purpose Feedback register 0 (GPF0)
without writing to the Physical Layer Control register or the
General Purpose register 0
read the general purpose feedback register 0 and write to
the system configuration register or the general purpose
register 0
the relevant General Purpose bit has been set; note 1
the relevant General Purpose bit has been cleared; note 1
0
11 to 0
GP0
General Purpose bits
1
0
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
12
A1, A0
RRS
RO
register address
Read Register Select
Read Only
1
1
1
read general purpose feedback register 1 (GPF1)
read the General Purpose Feedback register 1 (GPF1)
without writing to the Physical Layer Control register or the
General Purpose register 1
read the General Purpose Feedback register 1 and write to
the Physical Layer Control register or the General Purpose
register 1
the relevant General Purpose bit has been set
the relevant General Purpose bit has been cleared
0
11 to 0
GP1
General Purpose bits
1
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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