參數(shù)資料
型號: UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 55/81頁
文件大?。?/td> 323K
代理商: UJA1061
2004 Mar 22
55
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Table 23
Physical layer control and physical layer control feedback registers: status at reset
Table 24
Special mode register: status at reset
Table 25
General purpose and general purpose feedback register 0: status at reset
Table 26
General purpose and general purpose feedback register 1: status at reset
SYMBOL
NAME
POWER-ON
START-UP/
EXTERNAL RESET
RESTART
CPNC
CAN Partial Networking
Control
CAN Off-line Time
Control
CAN Transmitter Control
CAN Receiver Control
0 (no control)
no change
no change
COTC
1
no change
no change
CTC
CRC
0 (on)
no change
no change
no change
no change
0 (RXDC represents
CAN-bus signals)
0 (20 kbit/s)
0 (BAT14)
1 (enabled)
LSC
L42C
LWRC
LIN Slope Control
LIN 42 V control
LIN Wake-up Reset
Control
LIN Transmitter Control
no change
no change
no change
no change
no change
no change
LTC
0 (transmitter on)
no change
no change
SYMBOL
NAME
POWER-ON
START-UP/
EXTERNAL RESET
RESTART
ISDM
Initial Software
Development Mode
Error pin emulation
mode
Limp Home Mode
0 (no)
0 (no change)
0 (no change)
ERREM
0 (no)
no change
no change
LHM
0 (no)
0 (no change)
0 (no change)
SYMBOL
NAME
POWER-ON
START-UP/
EXTERNAL RESET
RESTART
GP0 11
general purpose bit 11:
1 for SBC identity; 0 for
general user purpose
general purpose
bits 10 to 7 (version)
general purpose
bits 6 to 0 (SBC type)
0
1
1
GP0
10 to 7
GP0 6 to 0
0011 (N1C)
no change
no change
0000001 (UJA1061)
no change
no change
SYMBOL
NAME
POWER-ON
START-UP/
EXTERNAL RESET
RESTART
GP1
general purpose bits
0
no change
no change
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