參數(shù)資料
型號: UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 65/81頁
文件大小: 323K
代理商: UJA1061
2004 Mar 22
65
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
I
OH
HIGH-level output
current
LOW-level output
voltage with V1
LOW
V
O
= V
V1
0.4 V; V1 = ON
1.6
0.5
mA
V
OL
I
OL
= 20
μ
A; V
V1
= 1.2 V
0
0.4
V
Enable output (pin EN)
I
OL
LOW-level output
current
HIGH-level output
current
LOW-level output
voltage
V
O
= 0.4 V
tbf
tbf
mA
I
OH
V
O
= V
V1
0.4 V
tbf
1.6
mA
V
OL
I
OL
= 20
μ
A; V
V1
= 1.2 V
0
0.4
V
Interrupt open-drain output (pin INTN)
I
OL
LOW-level output
current
CAN-bus transmit data input (pin TXDC)
V
IL
LOW-level input
voltage
V
IH
HIGH-level input
voltage
R
pu
TXDC pull-up
resistor
CAN-bus receive data output (pin RXDC)
I
OL
LOW-level output
current
I
OH
HIGH-level output
current
CAN-bus lines (pins CANH and CANL)
V
dif(CANH-CANL)
differentialreceiver
threshold voltage
V
O
= 0.4 V
1.6
tbf
mA
0.3
+0.3
×
V
V1
V
0.7
×
V
V1
V
V1
+ 0.3
V
V
TXDC
= 0 V
5
12
25
k
V
RXDC
= 0.4 V
1.6
tbf
mA
V
RXDC
= V
V1
0.4 V
tbf
1.6
mA
Active mode, On-line or Selective
Sleep mode; V
V2
= 5 V; no failures
and bus failures H//, L//, HxGND and
LxVCC
Active mode, On-line or Selective
Sleep mode; V
V2
= 5 V; bus failures
LxGND, LxBAT and HxL
Active mode, On-line or Selective
Sleep mode; V
V2
= 5 V; bus failures
HxBAT and HxVCC
Active mode, On-line or Selective
Sleep mode; V
V2
= 5 V
3.5
3.15
2.8
V
V
se(CANH)
pin CANH single
ended receiver
threshold voltage
pin CANL single
ended receiver
threshold voltage
detectionthreshold
voltage for bus
failuresHxBATand
LxBAT
pin CANH ground
shift detection
threshold voltage
1.45
1.7
1.95
V
V
se(CANL)
3.05
3.3
3.55
V
V
det(HxBAT)
,
V
det(LxBAT)
6.5
7.3
8.0
V
V
det(GSD)(CANH)
Active mode; V
V2
= 5 V
SPI bit GSDTH = logic 0
SPI bit GSDTH = logic 1
V
V
V
1.25
2.0
0.75
1.5
0.25
1.0
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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