參數(shù)資料
型號(hào)： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù)： 12/81頁(yè)
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
12
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
mce624
NORMAL
V1: ON
SYSINH: HIGH
V3: ON/OFF/cyclic
INH: HIGH/floating
CAN: active/auto
LIN: active
watchdog: window
EN: HIGH/LOW
FLASH
V1: ON
SYSINH: HIGH
V3: ON/OFF/cyclic
INH: HIGH/floating
CAN: active/auto
LIN: active
watchdog: time-out
EN: HIGH/LOW
STANDBY
V1: ON
SYSINH: HIGH
V3: ON/OFF/cyclic
INH: HIGH/floating
CAN: auto
LIN: off-line
watchdog: time-out/OFF
EN: HIGH/LOW
START-UP
V1: ON
SYSINH: HIGH
V3: ON/OFF/cyclic
INH: HIGH/floating
CAN: auto
LIN: off-line
watchdog: start-up
EN: LOW
RESTART
V1: ON
SYSINH: HIGH
V3: ON/OFF/cyclic
INH: floating
CAN: auto
LIN: off-line
watchdog: start-up
EN: LOW
FAIL-SAFE
V1: OFF
SYSINH: HIGH/floating
V3: unchanged
INH: floating
CAN: auto
LIN: off-line
watchdog: OFF
RSTN: LOW
EN: LOW
SLEEP
V1: OFF
SYSINH: HIGH/floating
V3: ON/OFF/cyclic
INH: floating
CAN: auto
LIN: off-line
watchdog: time-out/OFF
EN: LOW
out of Start-up/Restart/Sleep
wrong mode register code
OR interrupt ignored > 256 ms
OR (watchdog OFF AND IV > IV1(min) with reset option)
OR (watchdog time-out with reset option)
OR (Wake-up with reset option)
AND mode change
via SPI to Sleep with pending wake-up
user defined
reset pulse at pin RSTN
RSTN externally forced
falling edge
V3: unchanged
INH: floating
Flash entry =
disabled
out of
Normal/Standby/
Flash mode only
out of
Normal/Standby/
Flash mode only
V1 is active
AND V1 undervoltage
RSTN: LOW
INH: floating
BAT and GND connected
first time
long reset pulse at pin RSTN
V3: OFF
INH: floating
RSTN falling edge
OR (t > 256 ms and SDM = logic 0)
OR (wrong mode register code
AND SDM = logic 0)
OR SPI clock count < OR > 16
OR RSTN = LOW > 256 ms
OR (RSTN = HIGH AND V1 undervoltage)
(RSTN falling edge AND SDM = logic 0)
OR (t > 256 ms AND SDM = logic 0)
OR wrong mode register code
OR SPI clock count < OR > 16
Flash entry disabled
long reset pulse at pin RSTN
event
action
watchdog
trigger
mode change
via SPI
RSTN forced LOW
watchdog
trigger
mode change
via SPI
mode change
via SPI
mode change
via SPI
RSTN forced LOW
watchdog
trigger
init Normal mode
via SPI
successful
Flash entry = disabled
init Flash mode
via SPI
AND Flash entry enabled
Flash entry = disabled
wrong mode register code
OR [SDM = logic 0
AND (watchdog overflow
OR interrupt ignored > 256 ms)]
user defined
reset pulse at pin RSTN
init Normal mode
via SPI
successful
oscillator
fail
(RSTN = HIGH AND
RSTN driven LOW AND
SDM = logic 0) > 128 ms
Flash entry enabled
via mode sequence 111/001/111
OR wrong mode register code
OR [SDM = logic 0
AND (watchdog trigger too early
OR watchdog overflow
OR interrupt ignored > 256 ms)]
OR mode change
via SPI to Sleep with pending wake-up
user defined
reset pulse at pin RSTN
watchdog time-out
OR Wake-up
OR V3 overload
user defined
reset pulse at pin RSTN
Wake-up AND
recovered osc fail
long reset pulse at pin RSTN
reset code = Wake-up out
of fall-safe
(V1 is active AND
V1 undervoltage > 256 ms)
OR (V1 OK AND
RSTN = LOW > 256 ms)
Flash entry = disabled
Fig.3 Main state diagram UJA1061.
SDM = logic 0 represents the normal watchdog behaviour.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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