參數(shù)資料
型號: S70WS512N00BFWAB2
廠商: Spansion Inc.
英文描述: Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述: 同硅晶片堆疊多芯片產(chǎn)品(MCP)的512兆位(32兆× 16位)的CMOS 1.8伏,只有同時讀/寫,突發(fā)模式閃存
文件頁數(shù): 78/93頁
文件大?。?/td> 846K
代理商: S70WS512N00BFWAB2
March 14, 2005 S70WS512N00_00_A0
S70WS512N00 Based MCPs
79
A d v a n c e I n f o r m a t i o n
Notes:
1.
2.
3.
4.
5.
RDY(1) active with data (D8 = 1 in the Configuration Register).
RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
Figure shows the device not crossing a bank in the process of performing an erase or program.
RDY does not go low and no additional wait states are required if the Burst frequency is < = 66 MHz and the Boundary
Crossing bit (D14) in the Configuration Register is set to 0
Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz
CLK
Address (hex)
C124
C125
C126
C127
C127
C128
C129
C130
C131
D124
D125
D126
D127
D128
D129
D130
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C
7D
7E
7F
7F
80
81
82
83
latency
RDY(2)
latency
t
RACC
t
RACC
t
RACC
t
RACC
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