參數(shù)資料
型號(hào)： S70WS512N00BFWAB2
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫(xiě)，突發(fā)模式閃存
文件頁(yè)數(shù)： 67/93頁(yè)
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB2
68
S70WS512N00 Based MCPs
S70WS512N00_00_A0 March 14, 2005
A d v a n c e I n f o r m a t i o n
12.8
AC Characteristics
12.8.1
CLK Characterization
Note:
The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
Figure 12.6 CLK Characterization
12.8.2
Synchronous/ Burst Read
Notes:
1.
2.
3.
Addresses are latched on the first rising edge of CLK.
Not 100% tested.
The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
Parameter
Description
54 MHz
66 MHz
80 MHz
Unit
f
CLK
CLK Frequency
Max
54
66
80
MHz
t
CLK
CLK Period
Min
18.5
15.1
12.5
ns
t
CH
CLK High Time
Min
7.4
6.1
5.0
ns
t
CL
CLK Low Time
t
CR
CLK Rise Time
Max
3
3
2.5
ns
t
CF
CLK Fall Time
Parameter
Description
54 MHz
66 MHz
80 MHz
Unit
JEDEC
Standard
t
IACC
t
BACC
t
ACS
t
ACH
t
BDH
t
CR
t
OE
t
CEZ
t
OEZ
t
CES
t
RDYS
t
RACC
t
CAS
t
AVC
t
AVD
t
AOE
Latency
Max
80
ns
Burst Access Time Valid Clock to Output Delay
Max
13.5
11.2
9
ns
Address Setup Time to CLK (
Note 1
)
Min
5
4
ns
Address Hold Time from CLK (
Note 1
)
Min
7
6
ns
Data Hold Time from Next Clock Cycle
Min
4
3
ns
Chip Enable to RDY Valid
Max
13.5
11.2
9
ns
Output Enable to Output Valid
Max
13.5
11.2
ns
Chip Enable to High Z (
Note 2
)
Max
10
ns
Output Enable to High Z (
Note 2
)
Max
10
ns
CE# Setup Time to CLK
Min
4
ns
RDY Setup Time to CLK
Min
5
4
3.5
ns
Ready Access Time from CLK
Max
13.5
11.2
9
ns
CE# Setup Time to AVD#
Min
0
ns
AVD# Low to CLK
Min
4
ns
AVD# Pulse
Min
8
ns
AVD Low to OE# Low
Max
38.4
ns
tCLK
tCL
tCH
tCR
tCF
CLK
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