參數(shù)資料
型號： S70WS512N00BFWAB2
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 70/93頁
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB2
March 14, 2005 S70WS512N00_00_A0
S70WS512N00 Based MCPs
71
A d v a n c e I n f o r m a t i o n
Notes:
1.
Figure assumes 6 wait states for initial access and synchronous read.
2.
The Set Configuration Register command sequence has been written with CR8= 0; device outputs RDY one cycle before
valid data.
Figure 12.10 Linear Burst with RDY Set One Cycle Before Data
12.8.4
AC Characteristics—Asynchronous Read
Notes:
1.
2.
Not 100% tested.
The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
Parameter
Description
54 MHz
66 MHz
80 MHz
Unit
JEDEC
Standard
t
CE
Access Time from CE# Low
Max
80
ns
t
ACC
Asynchronous Access Time
Max
80
ns
t
AVDP
AVD# Low Time
Min
8
ns
t
AAVDS
Address Setup Time to Rising Edge of AVD#
Min
4
ns
t
AAVDH
Address Hold Time from Rising Edge of AVD#
Min
7
6
ns
t
OE
Output Enable to Output Valid
Max
13.5
ns
t
OEH
Output Enable Hold Time
Read
Min
0
ns
Data# Polling
Min
10
ns
t
OEZ
Output Enable to High Z (see Note)
Max
10
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
Da+ 1
t
BDH
Da
Da+ 2
Da+ 3
Da + n
OE#
Data
Addresses
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
AOE
6 wait cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
1
2
3
4
5
6
t
RDYS
t
BACC
t
CR
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