參數(shù)資料
型號： S70WS512N00BFWAB2
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 16/93頁
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB2
Publication Number
S70WS512N00_00
Revision
A
Amendment
0
Issue Date
March 14, 2005
General Description
The Spansion S29WS256/128/064N are Mirrorbit
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. These products can operate up to 80 MHz and use a single V
CC
of
1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better per-
formance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/ program/ erase ( 1.70– 1.95 V)
110 nm MirrorBit Technology
Simultaneous Read/ W rite operation w ith zero
latency
32-w ord W rite Buffer
Sixteen-bank architecture consisting of 16/ 8/ 4
Mw ords for W S256N/ 128N/ 064N, respectively
Four 16 Kw ord sectors at both top and bottom of
memory array
254/ 126/ 62 64 Kw ord sectors ( W S256N/ 128N/
064N)
Programmable burst read modes
— Linear for 32, 16 or 8 words linear read with or
without wrap-around
— Continuous sequential read mode
Flash products fabricated on 110 nm process technology. These burst
Secured Silicon Sector region consisting of 128
w ords each for factory and customer
20-year data retention ( typical)
Cycling Endurance: 100,000 cycles per sector
( typical)
RDY output indicates data available to system
Command set compatible w ith J EDEC ( 42.4)
standard
Performance Characteristics
Hardw are ( W P# ) protection of top and bottom
sectors
Dual boot sector configuration ( top and bottom)
Offered Packages
— WS064N: 80-ball FBGA (7 mm x 9 mm)
— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low V
CC
w rite inhibit
Persistent and Passw ord methods of Advanced
Sector Protection
W rite operation status bits indicate program and
erase operation completion
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash I nterface ( CFI )
I ndustrial Temperature range ( contact factory)
S29WS-N MirrorBit Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
ADVANCE
INFORMATION
Read Access Times
Speed Option ( MHz)
80
66
54
Max. Synch. Latency, ns (t
IACC
)
80
80
80
Max. Synch. Burst Access, ns (t
BACC
)
9
11.2
13.5
Max. Asynch. Access Time, ns (t
ACC
)
80
80
80
Max CE# Access Time, ns (t
CE
)
80
80
80
Max OE# Access Time, ns (t
OE
)
13.5
13.5
13.5
Current Consumption ( typical values)
Continuous Burst Read @ 66 MHz
35 mA
Simultaneous Operation (asynchronous)
50 mA
Program (asynchronous)
19 mA
Erase (asynchronous)
19 mA
Standby Mode (asynchronous)
20 μA
Typical Program & Erase Times
Single Word Programming
40 μs
Effective Write Buffer Programming (V
CC
) Per Word
9.4 μs
Effective Write Buffer Programming (V
ACC
) Per Word
6 μs
Sector Erase (16 Kword Sector)
150 ms
Sector Erase (64 Kword Sector)
600 ms
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