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參數(shù)資料
| 型號： | S70WS512N00BFWAB2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory |
| 中文描述： | 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 75/93頁 |
| 文件大?。?/td> | 846K |
| 代理商： | S70WS512N00BFWAB2 |
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S70WS512N00 Based MCPs
S70WS512N00_00_A0 March 14, 2005
A d v a n c e I n f o r m a t i o n
Notes:
1.
2.
3.
PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
In progress
and
complete
refer to status of program operation.
A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command
sequence unlock cycles.
Addresses are latched on the first rising edge of CLK.
Either CE# or AVD# is required to go from low to high in between programming command sequences.
The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.
The Configuration Register must be set to the Synchronous Read Mode.
4.
5.
6.
Figure 12.15 Synchronous Program Operation Timings
Note:
Use setup and hold times from conventional program operation.
Figure 12.16 Accelerated Unlock Bypass Programming Timing
OE#
CE#
Data
Addresses
WE#
CLK
V
CC
555h
PD
t
WC
t
WPH
t
WP
PA
t
VCS
t
DH
t
CH
ProIn
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
t
DS
t
AVDP
A0h
t
AS
t
CAS
t
AH
t
AVCH
t
CSW
t
AVSC
AVD#
CE#
AVD#
WE#
Addresses
Data
OE#
ACC
Don't Care
Don't Care
A0h
Don't Care
PA
PD
V
ID
V
IL
or V
IH
t
VID
t
VIDS
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| S70WS512N00BFWAB3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory |
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