參數(shù)資料
型號(hào)： S70WS512N00BFWAB2
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存
文件頁(yè)數(shù)： 11/93頁(yè)
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB2
March 14, 2005 S70WS512N00_00_A0
S70WS512N00 Based MCPs
9
A d v a n c e I n f o r m a t i o n
3
Input/Output Descriptions
Table 3.1
identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
Description
A23-A0
DQ15-DQ0
OE#
WE#
V
SS
NC
RDY
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read.
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at V
IL
or V
IH
while in asynchronous mode
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At V
, disables program and erase functions in the four outermost
sectors. Should be at V
IH
for all other conditions.
Accelerated input. At V
, accelerates programming; automatically places device in unlock bypass
mode. At V
IL
, disables all program and erase functions. Should be at V
IH
for all other conditions.
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode.
Flash 1.8 Volt-only single power supply.
Do Not Use
CLK
AVD#
F-RST#
F-WP#
F-ACC
F1-CE#
F2-CE#
F-VCC
DNU
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