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參數(shù)資料
| 型號： | S70WS512N00BFWAB2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory |
| 中文描述： | 同硅晶片堆疊多芯片產品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 23/93頁 |
| 文件大?。?/td> | 846K |
| 代理商： | S70WS512N00BFWAB2 |
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S70WS512N00 Based MCPs
S70WS512N00_00_A0 March 14, 2005
A d v a n c e I n f o r m a t i o n
Starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-
by-four address incurs the least number of additional wait states that occur after the initial
word. The number of additional wait states required increases for burst operations in which
the starting address is one, two, or three locations above the divisible-by-four address (i.e.,
where A[1:0] is 01, 10, or 11).
Boundary crossing: There is a boundary at every 128 words due to the internal architecture
of the device. One additional wait state must be inserted when crossing this boundary if the
memory bus is operating at a high clock frequency. Please refer to the tables below.
Clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation.
In all cases, with or without latency, the RDY output indicates when the next data is available to
be read.
Tables
8.2
–
8.6
reflect wait states required for S29WS256/128/064N devices. Refer to the
Con-
figuration Register
table (CR11 – CR14) and timing diagrams for more details.
Table 8.2 Address Latency (S29WS256N)
Word
Wait States
Cycle
0
x ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
x ws
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
x ws
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
x ws
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
Table 8.3 Address Latency (S29WS128N/S29WS064N)
Word
Wait States
Cycle
0
5, 6, 7 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
5, 6, 7 ws
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
5, 6, 7 ws
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
5, 6, 7 ws
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
Table 8.4 Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)
Word
Wait States
Cycle
0
7, 6 ws
D0
D1
D2
D3
1 ws
D4
D5
D6
D7
1
7, 6 ws
D1
D2
D3
1 ws
1 ws
D4
D5
D6
D7
2
7, 6 ws
D2
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
3
7, 6 ws
D3
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
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