參數(shù)資料
型號： S70WS512N00BFWAB2
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 25/93頁
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB2
26
S70WS512N00 Based MCPs
S70WS512N00_00_A0 March 14, 2005
A d v a n c e I n f o r m a t i o n
Figure 8.2 Synchronous Read
8.3.1
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addressable
memory location. The burst read mode continues until the system drives CE# high, or RESET=
V
IL
. Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad-
dress to the device.
If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-
sequent word line is not being programmed or erased, additional latency cycles are required as
reflected by the configuration register table (
Table 8.8
).
If the address crosses a bank boundary while the subsequent bank is programming or erasing,
the device provides read status information and the clock is ignored. Upon completion of status
read or program or erase operation, the host can restart a burst read operation using a new ad-
dress and AVD# pulse.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
Read Next Data
RD = DQ[15:0]
Wait t
+
Programmable Wait State Setting
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
End of Data
Yes
Crossing
Boundary
No
Yes
Completed
Delay X Clocks
Unlock Cycle 1
Unlock Cycle 2
RA = Read Address
RD = Read Data
Command Cycle
CR = Configuration Register Bits CR15-CR0
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
Note: Setup Configuration Register parameters
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