參數(shù)資料
型號： S70WS512N00BFWAB2
廠商： Spansion Inc.
英文描述： Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
中文描述： 同硅晶片堆疊多芯片產(chǎn)品（MCP）的512兆位（32兆× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 72/93頁
文件大?。?/td> 846K
代理商： S70WS512N00BFWAB2
March 14, 2005 S70WS512N00_00_A0
S70WS512N00 Based MCPs
73
A d v a n c e I n f o r m a t i o n
12.8.6
Erase/ Program Timing
Notes:
1.
2.
Not 100% tested.
Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both
Asynchronous and Synchronous program operation.
In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program
operation timing, addresses are latched on the rising edge of CLK.
See the
Erase and Programming Performance
section for more information.
Does not include the preprogramming time.
The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document
is Preliminary for the S29W256N.
3.
4.
5.
6.
Parameter
Description
54 MHz
66 MHz
80 MHz
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time (
Note 1
)
Min
80
ns
t
AVWL
t
AS
Address Setup Time (Notes
2
,
3
)
Synchronous
Min
5
ns
Asynchronous
0
ns
t
WLAX
t
AH
Address Hold Time (Notes
2
,
3
)
Synchronous
Min
9
ns
Asynchronous
20
t
AVDP
t
DS
t
DH
t
GHWL
t
CAS
t
CH
t
WP
t
WPH
t
SR/W
t
VID
t
VIDS
t
VCS
t
CS
t
AVSW
t
AVHW
t
AVSC
t
AVHC
t
CSW
t
WEP
t
SEA
t
ESL
t
PSL
t
ASP
t
PSP
AVD# Low Time
Min
8
ns
t
DVWH
t
WHDX
t
GHWL
Data Setup Time
Min
45
20
ns
Data Hold Time
Min
0
ns
Read Recovery Time Before Write
Min
0
ns
CE# Setup Time to AVD#
Min
0
ns
t
WHEH
t
WLWH
t
WHWL
CE# Hold Time
Min
0
ns
Write Pulse Width
Min
30
ns
Write Pulse Width High
Min
20
ns
Latency Between Read and Write Operations
Min
0
ns
V
ACC
Rise and Fall Time
V
ACC
Setup Time (During Accelerated Programming)
V
CC
Setup Time
CE# Setup Time to WE#
Min
500
ns
Min
1
μs
Min
50
μs
t
ELWL
Min
5
ns
AVD# Setup Time to WE#
Min
5
ns
AVD# Hold Time to WE#
Min
5
ns
AVD# Setup Time to CLK
Min
5
ns
AVD# Hold Time to CLK
Min
5
ns
Clock Setup Time to WE#
Min
5
ns
Noise Pulse Margin on WE#
Max
3
ns
Sector Erase Accept Time-out
Max
50
μs
Erase Suspend Latency
Max
20
μs
Program Suspend Latency
Max
20
μs
Toggle Time During Sector Protection
Typ
100
μs
Toggle Time During Programming Within a Protected Sector
Typ
1
μs
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