
Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
95
If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is
stuffed into the serial data output. This prevents the unintentional transmission of flag or abort
sequences.
Abort sequences (01111111 sequence where the 0 is transmitted first) can be continuously
transmitted at any time by setting a control bit. During packet transmission, an underrun situation
can occur if data is not written to the TDPR Transmit Data register before the previous byte has
been depleted. In this case, an abort sequence is transmitted, and the controlling processor is
notified via the UDR register bit. An abort sequence will also be transmitted if the user overflows
the FIFO with a packet of length greater than 128 bytes. Overflows where other complete
packets are still stored in the FIFO will not generate an abort. Only the packet which caused the
overflow is corrupted and an interrupt is generated to the user via the OVR register bit. The other
packets remain unaffected.
When the TDPR is disabled, a logical 1 (Idle) is inserted in the DS3 path maintenance data link.
11.23 SMDS PLCP Layer Transmitter (SPLT)
The SMDS PLCP Layer Transmitter (SPLT ) Block integrates circuitry to support DS3 based
PLCP frame insertion.
The SPLT automatically inserts the framing (A1, A2) and path overhead identification (POHID)
octets and provides registers or automatic generation of the F1, B1, G1, M2, M1 and C1 octets.
Registers are provided for the path user channel octet (F1) and the path status octet (G1). The bit
interleaved parity octet (B1) and the FEBE subfield are automatically inserted.
The DQDB management information octets, M1 and M2 are generated. The type 0 and type 1
patterns described in TA-TSY-000772 are automatically inserted. The type 1 page counter may
be reset using a register bit in the SPLT Configuration register. Note that this feature is not
required for the ATM Forum compliant DS3 UNI. For this application, the M1 and M2 octets
must be set to all zeros.
The PLCP transmit frame C1 cycle/stuff counter octet and the transmit stuffing pattern can be
referenced to the REF8K input pin, an internally generated 8 kHz reference synchronized to
SYSCLK, or a selected received PLCP frame pulse. Alternatively, a fixed stuffing pattern may be
inserted into the C1 cycle/stuff counter octet. In this mode, the C1 stuffing is generated based on
the received stuffing pattern as determined by the SPLR block.
When DS3 PLCP format is enabled, the C1 octet indicates the phase of the 375 μs nibble stuffing
opportunity cycle. During frame one of the three frame cycle, the pattern FFH is inserted in the
C1 octet, indicating a 13 nibble trailer length. During frame two, the pattern 00H is inserted,
indicating a 14 nibble trailer length. During frame three, the pattern 66H or 99H is inserted,
indicating a 13 or 14 nibble trailer length respectively.
The Zn, growth octets are set to 00H.