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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
44
Outgoing payload bytes may be optionally overwritten with the X
23
+ X
18
+ 1 PRBS pattern for
diagnosis of downstream equipment. The PRBS processor is configurable to handle all legal
mixes of STS-1/AU3, STS-3c/AU4, STS-12c/AU4-4c and STS-48c/AU4-16c in the incoming
TelecomBus interface. A time-slot interchange block is provided to allow arbitrary remapping of
streams at STS-1/AU3 granularity. Multicast is supported.
In the DS3 transmit direction, the S/UNI-MACH48 inserts DS3 framing, X, and P bits. When
enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are
provided for insertion of the FEAC channels and the Path Maintenance Data Links into the
appropriate overhead bits. Alarm Indication Signals can be inserted by using internal register
bits; other status signals such as the idle signal can be inserted when enabled by internal register
bits. The DS-3 frame is mapped into an STS-1 SPE as per Bellcore, ANSI, and ITU
specifications.
A single DS3 PRBS generator permits DS3 line error diagnostics at the far end for a selected DS3
channel.
In the PLCP transmit direction, the S/UNI-MACH48 provides overhead insertion using internal
registers, DS3 nibble stuffing, automatic BIP-8 octet generation and insertion and automatic far
end block error insertion. Diagnostic features for BIP-8 error, framing error and far end block
error insertion are also supported.
The S/UNI-MACH48 allows the ATM or POS data streams to be channelized into an STS-
48c/STM-16-16c or as any valid combination of STS-12c/STM-4c, STS-3c/STM-1, STS-1, and
DS3 channels. The STS-48c/STM-16-16c channel fills the entire bandwidth of the S/UNI-
MACH48 and is assigned to channel number 0. STS-12c/STM-4c channels can be assigned to
channels 0, 12, 24, and 36. STS-3c/STM-1 channels can be assigned within a range associated
with the STS-12 stream which it belongs to. STS-1/STM-0 and DS3 channels can be assigned to
any timeslot not already allocated to others but must also reside within the range of channel
values allocated to the STS-12 stream which it belongs to
When used to implement an ATM UNI or NNI, ATM cells are written to an internal FIFO using a
32-bit wide UTOPIA Level 3 or POS-PHY Level 3 (clocked up to 104 MHz) datapath interface.
The per-channel FIFO size is scalable from 2 cells to 48 cells in size. The total FIFO space
available is 192 cells. Idle/unassigned cells are automatically inserted when the internal FIFO
contains less than one complete cell. The S/UNI-MACH48 provides generation of the header
check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell
processing functions can be enabled or bypassed.
When used to implement a Packet over SONET/SDH or HDLC link, the S/UNI-MACH48 inserts
POS/HDLC frames into the SONET/SDH synchronous payload envelope or DS3 stream. Packets
to be transmitted are written into a FIFO through a 32-bit SATURN POS-PHY Level 3 (clocked
up to 104 MHz) system side interface. The per-channel FIFO size is scalable from 128 bytes to
3072 bytes in size. The total FIFO space available is 12,288 bytes. POS/HDLC frames are built
by inserting the flags, bit stuffs, control escape characters and the FCS fields. Either the CRC-
CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for
performance monitoring.