Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
7
11.28
ATM UTOPIA and Packet Over SONET POS-PHY System Interfaces (RXPHY and
TXPHY)...........................................................................................................100
11.29
SONET/SDH Inband Error Report Processor (SIRP).....................................102
11.30
Timeslot Interchange (STSI)...........................................................................102
11.31
Receive 8B/10B TelecomBus Decoder (R8TD)..............................................102
11.32
Transmit 8B/10B TelecomBus Encoder (T8TE)..............................................103
11.33
LVDS Overview...............................................................................................104
11.33.1
LVDS Receiver (RXLV)......................................................................105
11.33.2
LVDS Transmitter (TXLV)...................................................................105
11.33.3
LVDS Transmit Reference (TXREF)..................................................105
11.33.4
Data Recovery Unit (DRU).................................................................106
11.33.5
Parallel to Serial Converter (PISO)....................................................106
11.33.6
Clock Synthesis Unit (CSU)...............................................................106
11.34
JTAG Test Access Port ...................................................................................106
11.35
Microprocessor Interface................................................................................106
12
Normal Mode Register Description.........................................................................120
12.1
RCFP Register Summary...............................................................................249
12.2
TCFP Register Summary................................................................................271
12.3
RTDP Register Summary...............................................................................287
12.4
TTDP Register Summary................................................................................314
12.5
RCAS12 Register Summary...........................................................................335
12.6
TCAS12 Register Summary ...........................................................................340
12.7
DS3 Register Summary..................................................................................346
12.8
SIRP Register Summary.................................................................................422
12.9
PRGM Register Summary..............................................................................443
12.10
RHPP Register Summary...............................................................................473
12.11
STSI (IWTI, IPTI, OWTI, OPTI) Register Summary.......................................495
12.12
R8TD Register Summary ...............................................................................504
12.13
T8TE Register Summary................................................................................516
12.14
DLL Register Summary ..................................................................................526
12.15
Dropped Cell/Packet Counter Summary........................................................535
13
Test Features Description .......................................................................................543
13.1
Master Test and Test Configuration Registers................................................543
13.2
JTAG Test Port................................................................................................549
13.2.1
Boundary Scan Cells .........................................................................555