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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
24
Table 34 PRGD Generated Bit Error Rate Configurations ...........................................434
Table 35 PRGM Timeslot Selection..............................................................................445
Table 36 PRGM Monitor RAM Pages...........................................................................446
Table 37 PRGM Generator RAM Pages.......................................................................446
Table 38 PRGM Generator Master/Slave Configuration ..............................................461
Table 39 PRGM Monitor Master/Slave Configuration...................................................463
Table 40 TelecomBus Mode.........................................................................................521
Table 41 Test Mode Register Memory Map..................................................................543
Table 42 Instruction Register (Length - 3 bits)..............................................................549
Table 43 Identification Register ....................................................................................549
Table 44 Boundary Scan Register................................................................................549
Table 45 Serial TelecomBus 8B/10B Control Character Decoding..............................560
Table 46 Serial TelecomBus 8B/10B Control Character Encoding ..............................561
Table 47 PLCP Overhead Processing..........................................................................563
Table 48 PLCP Path Overhead Identifier Codes..........................................................564
Table 49 DS3 PLCP Trailer Length ..............................................................................564
Table 50 DS3 Frame Overhead Operation...................................................................566
Table 51 Standard Line-Side Timeslot Map .................................................................571
Table 52 Required System-Side Timeslot Map (TX48C = 0, RX48C = 0)....................572
Table 53 Required System-Side Timeslot Map (TX48C = 1, RX48C = 1)....................572
Table 54 Suggested FIFO Buffer Sizes........................................................................579
Table 55 SDQ FIFO_NUMBER Configuration..............................................................579
Table 56 SDQ Configuration Example.........................................................................580
Table 57 RXPHY Calendar Example............................................................................584
Table 58 RXPHY Calendar Recommended Setup.......................................................585
Table 59 SIRP Configuration ........................................................................................589
Table 60 STS-48c Configuration...................................................................................589
Table 61 Pseudo Random Pattern Generation (PS bit = 0) .........................................595
Table 62 Repetitive Pattern Generation (PS bit = 1) ....................................................596
Table 63 DS3 Overhead Bit Extraction.........................................................................614
Table 64 DS3 Overhead Bit Insertion...........................................................................615
Table 65 Absolute Maximum Ratings...........................................................................632
Table 66 D.C Characteristics........................................................................................633
Table 67 Microprocessor Interface Read Access (Figure 43) ......................................635
Table 68 Microprocessor Interface Write Access (Figure 44).......................................637