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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
83
11.8
DS3 Facility Data Link Receiver (RDLC)
The RDLC is a microprocessor peripheral used to receive LAPD/HDLC frames on the DS3 C-bit
parity Path Maintenance Data Link.
The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros
on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check
sequence (FCS).
In the address matching mode, only those packets whose first data byte matches one of two
programmable bytes or the universal address (all ones) are stored in the FIFO. The two least
significant bits of the address comparison can be masked for LAPD SAPI matching.
Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a
programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are
detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.
The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt
status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status
Register also indicates the abort, flag, and end of message status of the data just read from the
FIFO. On end of message, the Status Register indicates the FCS status and if the packet
contained a non-integer number of bytes.
11.9
SMDS PLCP Layer Receiver (SPLR)
The SMDS PLCP Layer Receiver (SPLR) Block integrates circuitry to support DS3 PLCP frame
processing. The SPLR provides framing for PLCP based transmission formats.
The SPLR frames to DS3 based PLCP frames with a maximum average reframe time of 22 μs.
Framing is declared (out of frame is removed) upon finding 2 valid, consecutive sets of framing
(A1 and A2) octets and 2 valid and sequential path overhead identifier (POHID) octets. While
framed, the A1, A2, and POHID octets are examined. OOF is declared when an error is detected
in both the A1 and A2 octets or when 2 consecutive POHID octets are found in error. LOF is
declared when an OOF state persists for more than 1 ms. If the OOF events are intermittent, the
LOF counter is decremented at a rate 1/12 of the incrementing rate. LOF is thus removed when
an in-frame state persists for more than 12 ms for a DS3 signal. When LOF is declared, PLCP
reframe is initiated.
Framing octet errors and path overhead identifier octet errors are indicated as frame errors. Bit
interleaved parity errors and far end block errors are indicated. The yellow signal bit is extracted
and accumulated to indicate yellow alarms. Yellow alarm is declared when 10 consecutive
yellow signal bits are set to logical 1; it is removed when 10 consecutive received yellow signal
bits are set to logical 0. The C1 octet is examined to maintain nibble alignment with the
incoming transmission system sublayer bit stream.