
Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
86
The RCAS-12 works on an STS-12/STM-4 data stream. It allows the STS-12/STM-4 data stream
to be split into DS3, STS-1/STM-0, STS-3c/STM-1, and STS-12c/STM-4 channels. STS-
48c/STM-16c data streams do not require processing by the RCAS blocks because no channel
division is required.
An RCAS-12 block can assign data streams to one of 12 possible channels. STS-12c/STM-4c
channels can be assigned to channels 0, 12, 24, and 36. STS-3c/STM-1 channels can be assigned
within a range associated with the STS-12 stream which it belongs to. STS-1/STM-0 and DS3
channels can be assigned to any timeslot not already allocated to others but must also reside
within the range of channel values allocated to the STS-12 stream to which it belongs.
An STS-48c stream will occupy all timeslots and will be transmitted across 4 RCAS12 blocks.
An STS-48c data stream must be assigned to channel 0.
The line side timeslot mappings can be arbitrary since the IWTI and IPTI blocks can be used to
move timeslots.
11.14 Receive Time-sliced Datacom Processor (RTDP)
The Receive Time-sliced Datacom Processor (RTDP) performs both ATM and HDLC processing.
It has the capability to process combinations of DS3, STS-1/STM-0, STS-3c/STM-1 channels
with aggregate throughput up to STS-12/STM-4 rates.
11.14.1 RTDP ATM Processor
In ATM mode, the RTDP performs ATM cell delineation, provides cell filtering based on
idle/unassigned cell detection and HCS error detection, and performs ATM cell payload
descrambling
Cell Delineation
Cell Delineation is the process of framing to ATM cell boundaries using the header check
sequence (HCS) field found in the cell header. The HCS is a CRC-8 calculation over the first 4
octets of the ATM cell header. When performing delineation, correct HCS calculations are
assumed to indicate cell boundaries. Cells are assumed to be byte-aligned to the SONET/SDH
SPE or DS3 PLCP paylaod, or nibbled aligned to the DS3 framing bit for direct-mapped ATM.
The cell delineation algorithm searches the 53 possible cell boundary candidates (or 106 possible
nibble-wide candidates for DS3) individually to determine the valid cell boundary location.
While searching for the cell boundary location, the cell delineation circuit is in the HUNT state.
When a correct HCS is found, the cell delineation state machine locks on the particular cell
boundary, corresponding to the correct HCS, and enters the PRESYNC state. The PRESYNC
state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will
be received within the next DELTA cells, at which time a transition back to the HUNT state is
executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered.
While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS
patterns are detected. In such an event a transition is made back to the HUNT state. The state
diagram of the delineation process is shown in Figure 7