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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
94
User control of each of the overhead bits in the DS3 frame is provided. Overhead bits may be
inserted on a bit-by-bit basis from a user supplied data stream by using the TOH, TOHINS,
TOHFP, TOHCH[5:0], and TOHVAL signals.
11.21 DS3 Bit Oriented Code Generator (XBOC)
The Bit Oriented Code Generator (XBOC) Block transmits 63 of the possible 64 bit oriented
codes (BOC) in the C-bit parity Far End Alarm and Control (FEAC) channel. A BOC is a 16-bit
sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which
is repeated as long as the code is not 111111. The code to be transmitted is programmed by
writing the XBOC Code Register. The 64th code (111111) is similar to the HDLC idle sequence
and is used to disable the transmission of any bit oriented codes. When transmission is disabled,
the FEAC channel is set to all ones.
The XBOC allows programmable repetitions of the BOC code. The desired BOC code can be
configured to repeat an integer number (N = 1 to 16) of times. An interrupt will signal when the
programmed BOC code has been latched and transmission started. The user can then disable
BOC transmission at this time to ensure the BOC code is only repeated N times. If the user does
not disable BOC transmission, the XBOC will transmit the BOC code another N times.
11.22 DS3 Facility Data Link Transmitter (TDPR)
The DS3 Facility Data Link Transmitter (TDPR) provides a serial data link for the C-bit parity
path maintenance data link. The TDPR HDLC facility data link transmission is controlled by the
external microprocessor. It performs all of the data serialization, CRC generation, zero-bit
stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-
CCITT frame check sequence (FCS) can optionally be appended, followed by flags. If the TDPR
transmit data FIFO underflows, an abort sequence is automatically transmitted.
When enabled, the TDPR continuously transmits flags (01111110) until data is ready to be
transmitted. Data bytes to be transmitted are written into the TDPR Transmit Data Register. The
TDPR automatically begins transmission of data once at least one complete packet is written into
its FIFO. All complete packets of data will be transmitted if no error condition occurs. After the
last data byte of a packet, the CRC FCS (if CRC insertion has been enabled) and a flag, or just a
flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the
transmission of flag characters until the next packet is available for transmission. The TDPR will
also force transmission of the FIFO data once the FIFO depth has surpassed the programmable
upper limit threshold. Transmission commences regardless of whether or not a packet has been
completely written into the FIFO. The user must be careful to avoid overflowing and
underflowing the FIFO. Underruns can only occur if the packet length is greater than the
programmed upper limit threshold because, in such a case, transmission will begin before a
complete packet is stored in the FIFO. All bytes which cause an overflow of the FIFO are
ignored.
An interrupt can be generated once the FIFO depth has fallen below a user configured lower
threshold as an indicator for the user to write more data. Interrupts can also be generated if the
FIFO underflows while transmitting a packet, when the FIFO is full, or if the FIFO is overrun.