
Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
84
11.10 PLCP Performance Monitor (PLCP PMON)
The PLCP Performance Monitor (PLCP PMON) Block interfaces directly to the SPLR to
accumulate bit interleaved parity error events, framing octet error events, and far end block error
events in saturating counters. When the PLCP framer (SPLR) declares loss of frame, bit
interleaved parity error events, framing octet error events, far end block error events, header
check sequence error events are not counted.
When an accumulation interval is signaled by a write to the PLCP PMON register address space
or to the S/UNI-MACH48 Identification and Global Monitor Update register, the PLCP PMON
transfers the current counter values into holding registers and resets the counters to begin
accumulating error events for the next interval. The counters are reset in such a manner that error
events occurring during the reset period are not missed.
11.11 DS3 Pseudo-Random Sequence Generator/Detector (PRGD)
The DS3 Pseudo-Random Sequence Generator/Detector (PRGD) block is a software
programmable test pattern generator, receiver, and analyzer. Two types of test patterns (pseudo-
random and repetitive) conform to ITU-T O.151. The PRGD is used for error diagnostic testing
on DS3 channels. There is only one PRGD block to service any one of the 48 possible DS3
channels. The PRGD receiver and transmitter can operate on independent DS3 channels.
The PRGD can be programmed to generate any pseudo-random pattern with length up to 2
32
-1
bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can
insert single bit errors or a bit error rate between 10
-1
to 10
-7
.
The PRGD can be programmed to check for the presence of the generated pseudo-random
pattern. The PRGD can perform an auto-synchronization to the expected pattern, and generate
interrupts on detection and loss of the specified pattern. The PRGD can accumulate the total
number of bits received and the total number of bit errors in two saturating 32-bit counters. The
counters accumulate over an interval defined by writes to the S/UNI-MACH48 Global Monitor
Update register or by writes to a PRGD accumulation register. When an accumulation is forced
by either method, then the holding registers are updated, and the counters reset to begin
accumulating for the next interval. The counters are reset in such a way that no events are
missed. The data is then available in the holding registers until the next accumulation. In
addition to the two counters, a record of the 32 bits received immediately prior to the
accumulation is available.
The PRGD may also be programmed to check for repetitive sequences. When configured to
detect a pattern of length N bits, the PRGD will load N bits from the detected stream, and
determine whether the received pattern repeats itself every N subsequent bits. Should it fail to
find such a pattern, it will continue loading and checking until it finds a repetitive pattern. All the
features (error counting, auto-synchronization, etc.) available for pseudo-random sequences are
also available for repetitive sequences. Whenever a PRGD accumulation is forced, the PRGD
stores a snapshot of the 32 bits received immediately prior to the accumulation. This snapshot
may be examined in order to determine the exact nature of the repetitive pattern received by
PRGD.