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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
581
UL3/PL3
Channel #
PHYID
[5:0]
BW
Size
(Blocks/
Cells)
FIFO_BS
[1:0]
Bank
FIFO_
NUMBER
[5:0]
Starting
Block
BLOCK_
PTR[4:0]
37
0x25
STS-3c
16/4
‘b01
3
0x31
0x10
0x2
38
0x26
STS-3c
16/4
‘b01
3
0x32
0x20
0x4
39
0x27
STS-3c
16/4
‘b01
3
0x33
0x30
0x6
Note that this configuration leaves some spare capacity in Bank 3. Each bank has the capacity to
handle 12 FIFOs of 16 blocks each. In the example, only 16 FIFOs have been assigned and they
take up a sum of 640 blocks. This is because four STS-3c FIFOs have been configured to hold
only 16 blocks each instead of 48. Because of the way their BLOCK_PTR[4:0] have been set the
FIFO corresponding to Channel #39 can expand it’s FIFO sizes to be 48 blocks without affecting
other FIFOs. However, channels 36-38 cannot expand without moving the other channels to
make room for the larger FIFO. See Section 14.14 for details on SDQ dynamic reconfiguration.
When configuring/modifying SDQ for a PHY ID, the FIFO# should be set accordingly. Different
PHY IDs cannot have the same FIFO# otherwise, the configuration of the other PHY will be
overwritten.
The SDQ cannot detect errors due to user misconfiguration. If the user sets up FIFOs that overlap
each other, or do not start at a Block number that is an integral multiple of the size of the FIFO,
the results will be unpredictable.
14.14 RXSDQ and TXSDQ Dynamic Reconfiguration
Each PHY connected to a FIFO can have a depth of 16, 48 or 192 Blocks. The SDQ allows the
reconfiguration of these PHY to different sizes (for example: the aggregation of four adjacent 12
Block FIFOs into one 48 Block FIFO) without dropping any cells or packets in FIFOs belonging
to other PHYs. In order to perform a reconfiguration, the FIFOs being reconfigured should first
be disabled (ENABLE = 0) using the FIFO Indirect Configuration register. When disabled, the
FIFO will cease to accept any new data, but will continue to drain all existing blocks to the read
interface. The user should manually empty the FIFO (by writing a 1 to the FLUSH bit in the
FIFO Indirect Address register). Once all the FIFOs that need to be reconfigured are empty, the
user must manually clear the FLUSH bit, then write the new configuration by recalculating the
FIFO_NUMBER[5:0] and BLOCK_PTR[4:0] bits, changing the FIFO_BS[1:0] bits, and finally
in a separate indirect write, setting the appropriate ENABLE bit. This procedure ensures that the
FIFOs not being reconfigured are not affected in any way, and allows the ones being reconfigured
to not drop any pre-existing data.
As indicated, the user can only aggregate adjacent FIFOs. However, any individual FIFO can be
expanded as long as there is no overlap between FIFOs due to this expansion. The user can
reduce a FIFO’s size at any time as this will not cause an overlap.
Care should be taken to insure that the ENABLE bit is not set until all other configuration
changes have already been written into the FIFO by applying the following procedure:
1. Set indirect data values with ENABLE = 0