
Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
68
Pin Name
Type
Pin No.
Function
Receive Serial TelecomBus Interface (17 Signals)
RPWRK[4]
RNWRK[4]
RPWRK[3]
RNWRK[3]
RPWRK[2]
RNWRK[2]
RPWRK[1]
RNWRK[1]
Analog
LVDS
Input
R3
R2
P2
P1
N3
N2
M4
M3
Receive Working Serial Data.
The differential receive
working serial data links (RPWRK[3:0]/RNWRK[3:0])
carries the receive SONET/SDH STS-48 frame data
from an upstream working source, in bit serial format.
Each differential pair carries a constituent STS-12 of
the receive working stream.
Data on RPWRK/RNWRK is encoded in an 8B/10B
format extended from IEEE Std. 802.3. The 8B/10B
character bit ‘a(chǎn)’ is transmitted first and the bit ‘j’ is
transmitted last.
The four differential pairs in RPWRK[3:0]/RNWRK[3:0]
are frequency locked but not phase locked.
RPWRK[3:0]/RNWRK[3:0] are nominally 777.6 Mbps
data streams. RPWRK[3:0]/RNWRK[3:0] may be left
floating, or be tied to ground if unused.
RPPROT[4]
RNPROT[4]
RPPROT[3]
RNPROT[3]
RPPROT[2]
RNPROT[2]
RPPROT[1]
RNPROT[1]
Analog
LVDS
Input
AA2
AA1
Y2
Y1
Y4
Y3
V4
V3
Receive Protect Serial Data.
The differential receive
protection serial data links
(RPPROT[3:0]/RNPROT[3:0]) carries the receive
SONET/SDH STS-48 frame data from an upstream
protection source, in bit serial format. Each differential
pair carries a constituent STS-12 of the receive
protection stream. Data on RPPROT/RNPROT is
encoded in an 8B/10B format extended from IEEE Std.
802.3. The 8B/10B character bit ‘a(chǎn)’ is transmitted first
and the bit ‘j’ is transmitted last. The four differential
pairs in RPPROT[3:0]/RNPROT[3:0] are frequency
locked but not phase locked.
RPPROT[3:0]/RNPROT[3:0] are nominally 777.6 Mbps
data streams. RPPROT[3:0]/RNPROT[3:0] may be left
floating, or be tied to ground if unused.
RJ0FP
Input
AV32
Receive Serial Interface Frame Pulse.
The receive
serial interface frame pulse signal (RJ0FP) provides
system timing of the receive serial interface. RJ0FP is
expected to be set high once every 9720 SYSCLK
cycles, or multiple thereof, to indicate the J0 frame
boundary. The RJ0DLY[13:0] register bits are used to
align the J0 character on the Receive Serial
TelecomBus interface (RPWRK[3:0]/RNWRK[3:0] and
RPPROT[3:0]/RNPROT[3:0]) with RJ0FP.
This pin is only used when the LVDS serial interface is
enabled (SER_EN is logic 1). RJ0FP is sampled on
the rising edge of SYSCLK.