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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
21
List of Figures
Figure 1 Multi-Service ATM/POS Switch Port Application..............................................35
Figure 2 Pin Diagram – Bottom View..............................................................................46
Figure 3 Pin Diagram – Bottom View (Top,Left Quadrant).............................................47
Figure 4 Pin Diagram – Bottom View (Top, Right Quadrant)..........................................48
Figure 5 Pin Diagram – Bottom View (Bottom, Left Quadrant).......................................49
Figure 6 Pin Diagram – Bottom View (Bottom, Right Quadrant) ....................................50
Figure 7 Cell Delineation State Diagram.........................................................................87
Figure 8 PPP/HDLC Over SONET Frame Format..........................................................89
Figure 9 CRC Decoder....................................................................................................90
Figure 10 CRC Generator...............................................................................................98
Figure 11 Generic LVDS Link Block Diagram...............................................................104
Figure 12 Input Observation Cell (IN_CELL)................................................................555
Figure 13 Output Cell (OUT_CELL)..............................................................................556
Figure 14 Bidirectional Cell (IO_CELL).........................................................................556
Figure 15 Layout of Output Enable and Bidirectional Cells..........................................557
Figure 16 S/UNI-MACH48 Conceptual Regions...........................................................559
Figure 17 DS3 PLCP Frame Format.............................................................................562
Figure 18 DS3 Frame Structure....................................................................................565
Figure 19 ATM Mapping into a STS-12c/STM-4c SPE.................................................567
Figure 20 POS Mapping into a STS-12c/STM-4c SPE.................................................567
Figure 21 A 52 Byte ATM Data Structure .....................................................................569
Figure 22 A 63 Byte Packet Data Structure..................................................................570
Figure 23 PRGD Pattern Generator..............................................................................594
Figure 24 Typical DS3 FDL Data Frame.......................................................................603
Figure 25 Example DS3 FDL Multi-Packet Operational Sequence..............................604
Figure 26 Boundary Scan Architecture.........................................................................607
Figure 27 TAP Controller Finite State Machine ............................................................609
Figure 28 Analog Power Supply Filtering Circuits ........................................................613
Figure 29 DS3 Overhead Extraction.............................................................................614
Figure 30 DS3 Overhead Insertion ...............................................................................615
Figure 31 Incoming Parallel TelecomBus Timing .........................................................617
Figure 32 Outgoing Parallel TelecomBus.....................................................................619
Figure 33 Receive Serial TelecomBus Link Timing......................................................620