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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
23
List of Tables
Table 1 Asynchronous DS3 Mapping to STS-1 (STM-0/AU3)........................................78
Table 2 DS3 AIS Format.................................................................................................79
Table 3 Byte Destuffing...................................................................................................89
Table 4 Byte Stuffing.......................................................................................................98
Table 5 Register Memory Map......................................................................................107
Table 6 Receive Timeslot Configuration for Different Traffic Types.............................126
Table 7 Valid Receive Timeslot Mappings....................................................................127
Table 8 Transmit Timeslot Configuration for Different Traffic Types............................133
Table 9 Valid Transmit Timeslot Mappings...................................................................134
Table 10 8 KHz Reference Selection............................................................................142
Table 11 DS3 LOF Integration Period Configuration....................................................145
Table 12 Incoming STSI Mapping Modes.....................................................................149
Table 13 Outgoing STSI Mapping Modes.....................................................................150
Table 14 Functionality of the CRC_SEL[1 0] Register Bits...........................................251
Table 15 Average STS-x cell period versus LCD integration period ............................259
Table 16 Selection of the number of FLAG Bytes ........................................................273
Table 17 CRC Mode Selection .....................................................................................273
Table 18 Functionality of the CRC_SEL[1 0] Register Bits...........................................291
Table 19 Selection of the number of Flag Bytes...........................................................318
Table 20 CRC Mode Selection .....................................................................................319
Table 21 RCAS12 Timeslot Mode Selection ................................................................338
Table 22 TCAS12 Timeslot Mode Selection.................................................................344
Table 23 DS3 Base Address Assignment.....................................................................346
Table 24 SPLR FORM[1 0] Configurations...................................................................349
Table 25 PLCP LOF Declaration/Removal Times........................................................354
Table 26 SPLT FORM[1 0] Configurations...................................................................357
Table 27 DS3 FRMR AIS Configurations......................................................................368
Table 28 RDLC PBS[2 0] Data Status..........................................................................381
Table 29 SIRP RDI and REI Reporting Modes.............................................................424
Table 30 SIRP RDI Settings .........................................................................................424
Table 31 SIRP RDI Maintenance..................................................................................424
Table 32 SIRP RDI Priority Schemes...........................................................................427
Table 33 PRGD Pattern Detector Register Configuration ............................................429