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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
582
2. Write desired indirect address with FLUSH = 1
3. Wait until EMPTY is polled as 1
4. Set indirect data values
5. Write indirect address with FLUSH = 0
6. When ready, set indirect data values with ENABLE = 1
7. Write desired indirect address
For step 4, the user must read all indirect data values for the desired PHY and write them back
modifying only the ENABLE bit by setting it to logic 1. Note that this procedure of reading all
indirect data values and writing all indirect data values for each indirect write performed is
required to maintain the desired configuration for the SDQ FIFOs.
14.15 TXSDQ Buffer Available Operation
For each of the FIFOs configured in the TXSDQ, a Buffer Available (BA[p]) bit indicates
whether or not the FIFO p can accept more data. The BA[p] status is given (BA[p] = 1) when
the TXSDQ can accommodate at least another injection of BT[4:0] + 1 blocks into its FIFO p.
When the number of blocks available in FIFO p is less than (BT[4:0] + 1), then BA[p] is
deasserted (BA[p] = 0). At this point, no more new data can be accepted, but the current
transaction completes (if BT[p] is not set at the maximum for FIFO p). Eventually, when some of
the data in FIFO p is drained by the read interface, the available FIFO space will equal or exceed
BT[4:0] + 1. BA[p] is asserted when this condition is reached. The BA[p] state is reflected by
the TCA and STPA and PTPA output signals on the Utopia L3 and POS-PHY L3 interfaces when
PHY p is selected and/or polled.
In setting the TXSDQ buffer available threshold BT[4:0], the maximum data burst size from the
upstream device must be taken into account. Section 15.8.2 describes how to program BT[4:0] to
keep the upstream device from overflowing the TXSDQ FIFO. In general, the following formula
applies:
(BT[4:0] + 1) max burst size from upstream device + system application margin
The values of BT[4:0] and DT[7:0] in the TXSDQ Indirect Data and Buffer Available Thresholds
register must be set so that:
(DT[7:0] + 1) + (BT[4:0] + 1)
≤
FIFO size
The FIFO size is set using the FIFO_BS[1:0] register bits in the TXSDQ FIFO Indirect
Configuration register and DT[7:0] is the TXSDQ is set in the TXSDQ Indirect Data and Buffer
Available Thresholds register. This constraint keeps the FIFO from entering a state where the
TXSDQ cannot sustain a new burst from the upstream device and the downstream TCFP or TTDP
block does not have enough data to initiate a transfer.