參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 99/158頁
文件大小： 1020K
代理商： MC68HC908RK2DW
COP Control Register
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
45
4.3.8 COPRS
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See
4.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
4.5 Interrupts
The COP does not generate CPU interrupt requests.
4.6 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ pin or on the RST pin.
4.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
4.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit (see Chapter 3 Configuration Register (CONFIG)) enables the STOP instruction. To
prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by
clearing the STOP bit.
4.8 COP Module During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on the RST pin.
Address:
$FFFF
Bit 7
654321
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 4-2. COP Control Register (COPCTL)
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