參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 17/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Low-Power Modes
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
113
10.5.2 Reset
All reset sources always have higher priority than interrupts and cannot be arbitrated.
10.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See 12.2 Break Module (BRK).) The SIM puts the CPU into the break state by
forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how
each module is affected by the break state.
10.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
10.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power- consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described here. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
10.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 10-12
shows the timing for wait mode entry.
Figure 10-12. Wait Mode Entry Timing
WAIT ADDR + 1
SAME
IAB
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
WAIT ADDR
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
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