參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 153/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Low-Voltage Inhibit (LVI)
MC68HC908RK2 Data Sheet, Rev. 5.1
94
Freescale Semiconductor
8.3.1 False Trip Protection
The VDD pin level is digitally filtered to reduce false dead battery detection due to power supply noise. For
the LVI module to reset due to a low-power supply, VDD must remain at or below the VLVR level for a
minimum 32–40 CGMXCLK cycles. See Table 8-1.
8.3.2 Short Stop Recovery Option
The LVI has an enable time of tEN. The system stabilization time for power-on reset and long stop
recovery (both 4096 CGMXCLK cycles) gives a delay longer than the LVI enable time for these startup
scenarios. There is no period where the MCU is not protected from a low-power condition. However, when
using the short stop recovery configuration option, the 32 CGMXCLK delay must be greater than the LVI
turn on time to avoid a period in startup where the LVI is not protecting the MCU.
NOTE
The LVI is enabled automatically after reset or stop recovery, if the
LVISTOP of the CONFIG register is set. See Chapter 3 Configuration
8.4 LVI Status Register
The LVI status register flags VDD voltages below theVLVR and VLVS levels.
LVIOUT — LVI Output Bit
The read-only flag becomes set when the VDD voltage falls below the VLVR voltage for 32 to 40
CGMXCLK cycles. Reset clears the LVIOUT bit.
LOWV— LVI Low Indicator Bit
This read-only flag becomes set when the LVI is detecting VDD voltage below the VLVS threshold.
Table 8-1. LOWV Bit Indication
VDD
Result
At Level:
For Number of CGMXCLK Cycles:
VDD > VLVR
ANY
Filter counter remains clear
VDD < VLVR
< 32 CGMXCLK cycles
No reset, continue
counting CGMXCLK
VDD < VLVR
Between 32 & 40 CGMXCLK cycles
LVI may generate
a reset after 32 CGMXCLK
VDD < VLVR
> 40 CGMXCLK cycles
LVI is guaranteed to generate a reset
Address: $FE0F
Bit 7
654321
Bit 0
Read:
LVIOUT
0
LOWV
00000
Write:
Reset:
00000000
= Unimplemented
Figure 8-2. LVI Status Register (LVISR)
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