參數(shù)資料
型號: MC68HC908RK2DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 124/158頁
文件大?。?/td> 1020K
代理商: MC68HC908RK2DW
Internal Clock Generator Module (ICG)
MC68HC908RK2 Data Sheet, Rev. 5.1
68
Freescale Semiconductor
ICLK). When switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock
being switched to must also be stable (ICGS or ECGS set).
Figure 6-6. Clock Selection Circuit Block Diagram
6.3.5.2 Clock Switching Circuit
To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes
the clocks are completely asynchronous, so a synchronizing circuit is required to make the transition (see
Figure 6-7). When the clock select bit is changed, the switch will continue to operate off the original clock
for between 1 and 2 cycles as the select input transitions through one side of the synchronizer. Next, the
output will be held low for between 1 and 2 cycles of the new clock as the select input transitions through
the other side. Then the output starts switching at the new clock’s frequency. This transition guarantees
that no glitches will be seen on the output even though the select input may change asynchronously to
the clocks. The unpredictably of the transition period is a necessary result of the asynchronicity.
Figure 6-7. Synchronizing Clock Switcher Circuit Diagram
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
SELECT
OUTPUT
SYNCHRONIZING
CLOCK
SWITCHER
DIV2
NAME
TOP LEVEL SIGNAL
REGISTER BIT
MODULE SIGNAL
RESET
ECLK
EOFF
ICLK
IOFF
VSS
CS
CGMOUT
CGMXCLK
FORCE_I
ECLK
EOFF
OUTPUT
DQ
CK
DFF
QB
SELECT
ICLK
DQ
CK
DFF
QB
DQ
CK
DFF
QB
DQ
CK
DFF
QB
FORCE_E
FORCE_I = Force internal; reset condition
FORCE_E = Force external
IOFF
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