參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 132/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Usage Notes
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
75
6.4.7 Improving Settling Time
The settling time of the internal clock generator can be vastly improved if an external clock source can be
used during the settling time. When the internal clock generator is disabled (ICGON is low), the DDIV[3:0]
and DSTG[7:0] bits can be written. Then, when the internal clock generator is re-enabled, the clock period
will automatically start at the point written in the DDIV and DSTG bits.
Since a change in the DDIV and DSTG bits only cause a change in the clock period relative to the starting
point, the starting point must first be captured. The initial clock period can be expressed as in the next
example, where
τX is a process, temperature, and voltage dependent constant and DDIV1 and DSTG1
are the values of DDIV and DSTG when operating at
τ1.
Finding the new values for DDIV and DSTG is easy if the new clock period is a binary multiple or fraction
of the original. In this case, DSTG is unchanged and DDIV2 is DDIV1 + log2(τ2/τ1).
If the new clock period is not a binary multiple or fraction of the original, both DSTG and DDIV may need
to change according to these equations:
If DSTG2 is greater than 255:
The software required to do this is relatively simple, since most of the math can be done before coding
because the initial and final clock periods are known. An example of how to code this in assembly code
is shown in Figure 6-10. This example is for illustrative purposes only and does not represent a valid
syntax for any particular assembler.
6.4.8 Trimming Frequency on the Internal Clock Generator
The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the
frequency comparator indicate zero error, will vary as much as
±25% due to process, temperature, and
voltage dependencies. These dependencies are in the voltage and current references, the offset of the
comparators, and the internal capacitor. The voltage and temperature dependencies have been designed
to be a maximum of approximately
±1% error. The process dependencies account for the rest.
Fortunately, for an individual part, the process dependencies are constant. An individual part can operate
at approximately
±2% variance from its unadjusted operating point over the entire specification range of
the application. If the unadjusted operating point can be changed, the entire variance can be limited
to
±2%.
τ
1
τ
X
2
DDIV1
DSTG1
=
DVFACT
int
τ
2 τ1
()
log
2
()
log
-----------------------------
=
DDIV2
DDIV1
DVFACT
+
=
DSFACT
τ
2 τ1
()
2
DDIV2
DDIV1
–
()
----------------------------------------------------
=
DSTG2
DSFACT DSTG1
=
DDIV2
1
+
=
DSTG2
2
---------------------
=
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