參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 12/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
SIM Counter
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
109
10.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
10.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the internal clock generation module
(ICG) to drive the bus clock state machine.
10.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
CONFIG register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal applications should use the full
stop recovery time, that is, with SSREC cleared.
10.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. See 10.6.2 Stop Mode for details. The SIM counter is
free-running after all reset states. See 10.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
10.5 Program Exception Control
Normal, sequential program execution can be changed in three different ways:
1.
Interrupts:
a.
Maskable hardware CPU interrupts
b.
Non-maskable software interrupt instruction (SWI)
2.
Reset
3.
Break interrupts
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