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參數(shù)資料
| 型號(hào)： | MC68HC908RK2DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁(yè)數(shù)： | 145/158頁(yè) |
| 文件大?。?/td> | 1020K |
| 代理商： | MC68HC908RK2DW |
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Functional Description
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
87
7.3.2 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch. If the MODEI bit is set, the IRQ pin is both falling-edge sensitive and
low-level sensitive. With MODEI set, both of these actions must occur to clear the IRQ latch:
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACKI bit in
the IRQ and keyboard status and control register (INTKBSCR). The ACKI bit is useful in
applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACKI
bit can also prevent spurious interrupts due to noise. Setting ACKI does not affect subsequent
transitions on the IRQ pin. A falling edge on IRQ that occurs after writing to the ACKI bit latches
another interrupt request. If the IRQ mask bit, IMASKI, is clear, the CPU loads the program counter
with the vector address at locations $FFFA and $FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic 1 can occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the
MODEI control bit, thereby clearing the interrupt even if the pin stays low.
If the MODEI bit is clear, the IRQ pin is falling-edge sensitive only. With MODEI clear, a vector fetch or
software clear immediately clears the IRQ latch.The IRQF bit in the INTKBSCR register can be used to
check for pending interrupts. The IRQF bit is not affected by the IMASKI bit, which makes it useful in
applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
7.3.3 KBI Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ or keyboard interrupt latchs can be
cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software
to clear the latches during the break state. See 10.7.3 SIM Break Flag Control Register.
To allow software to clear the IRQ or keyboard latchs during a break interrupt, write a 1 to the BCFE bit.
If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
writing to the ACKI or ACKK bits in the IRQ and keyboard status and control register during the break
state has no effect on the IRQ or keyboard latchs.
7.3.4 Keyboard Interrupt Pins
Writing to the KBIE6–KBIE1 bits in the keyboard interrupt enable register independently enables or
disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its
internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches an IRQ/keyboard
interrupt request.
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