參數(shù)資料
型號(hào)： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 18/158頁
文件大小： 1020K
代理商： MC68HC908RK2DW
System Integration Module (SIM)
MC68HC908RK2 Data Sheet, Rev. 5.1
114
Freescale Semiconductor
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is 0, then the computer operating properly module (COP) is enabled and remains active in
wait mode.
Figure 10-13 and Figure 10-14 show the timing for WAIT recovery.
Figure 10-13. Wait Recovery from Interrupt or Break
10.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
Figure 10-14. Wait Recovery from Internal Reset
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the CONFIG register.
If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32.
This is ideal for applications using canned oscillators that do not require long startup times from stop
mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
$6E0C
$6E0B
$00FF
$00FE
$00FD
$00FC
$A6
$01
$0B
$6E
$A6
IAB
IDB
EXITSTOPWAIT
Note: EXITSTOPWAIT =
RST pin or CPU interrupt orR break interrupt
IAB
IDB
RST
$A6
$6E0B
RSTVCTH
RSTVCTL
$A6
CGMXCLK
32
CYCLES
32
CYCLES
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