參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 3/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Input/Output (I/O) Ports
MC68HC908RK2 Data Sheet, Rev. 5.1
100
Freescale Semiconductor
9.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the six port B pins.
PTB[5:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
TCH1 — Timer Channel I/O Bit
The PTB4/TCH1 pin is the TIM channel 1input capture/output compare pin. The edge/level select bits,
ELS1B:ELS1A, determine whether the PTB4/TCH1 pin is a timer channel I/O or a general-purpose I/O
TCH0 — Timer Channel I/O Bit
The PTB2/TCH0 pin is the TIM channel 0 input capture/output compare pin. The edge/level select bits,
ELS0B:ELS0A, determine whether the PTB2/TCH0 pin is a timer channel I/O or a general-purpose I/O
TCLK — Timer Clock
The PTB3/TCLK pin is the external clock input for TIM. The prescaler select bits, PS[2:0], select
PTB3/TCLK as the TIM clock input. (See 11.8.1 TIM Status and Control Register.) When not selected
as the TIM clock, PTB3/TCLK is available for general-purpose I/O.
MCLK — Bus Clock
The bus clock (MCLK) is driven out of pin PTB0/MCLK when enabled by the MCLKEN bit in port B data
direction register bit 7.
9.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Address:
$0001
Bit 7
6
5
4321
Bit 0
Read:
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Write:
Reset:
Unaffected by reset
Alternate
Functions:
TCH1
TCLK
TCH0
MCLK
= Unimplemented
Figure 9-5. Port B Data Register (PTB)
Address:
$0005
Bit 7
654
321
Bit 0
Read:
MCLKEN
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
0000
= Unimplemented
Figure 9-6. Data Direction Register B (DDRB)
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