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| 型號： | MC68HC908RK2DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 130/158頁 |
| 文件大小： | 1020K |
| 代理商： | MC68HC908RK2DW |
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Usage Notes
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
73
6.4.5 Switching Internal Clock Frequencies
The frequency of the internal clock (ICLK) may need to be changed for some applications. For example,
if the reset condition does not provide the correct frequency, or if the clock is slowed down for a low-power
mode (or sped up after a low-power mode), the frequency must be changed by programming the internal
clock multiplier factor (N). The frequency of ICLK is N times the frequency of IBASE, which is 307.2 kHz
±25%.
Before switching frequencies by changing the N value, the clock monitor must be disabled. This is
because when N is changed, the frequency of the low-frequency base clock (IBASE) will change
proportionally until the digital loop filter has corrected the error. Since the clock monitor uses IBASE, it
could erroneously detect an inactive clock. The clock monitor cannot be re-enabled until the internal clock
is stable again (ICGS is set).
NOTE
There is no hardware mechanism to prevent changing bus frequency
dynamically. Be careful when changing bus frequency and consider the
impact on the system.
This flow is an example of how to change the clock frequency:
1.
Verify there is no clock monitor interrupt by reading the CMF bit.
2.
Turn off the clock monitor.
3.
If desired, switch to the external clock (see 6.4.1 Switching Clock Sources).
4.
Change the value of N.
5.
Switch back to internal (see 6.4.1 Switching Clock Sources), if desired.
6.
Turn on the clock monitor (see 6.4.2 Enabling the Clock Monitor), if desired.
6.4.6 Nominal Frequency Settling Time
Because the clock period of the internal clock (ICLK) is dependent on the digital loop filter outputs (DDIV
and DSTG) which cannot change instantaneously, ICLK will temporarily operate at an incorrect clock
period when any of the operating condition changes. This happens whenever the part is reset, the ICG
multiply factor (N) is changed, the ICG trim factor (TRIM) is changed, or the internal clock is enabled after
inactivity (STOP or disabled operation). The time that the ICLK takes to adjust to the correct period is
known as the settling time.
Settling time depends primarily on how many corrections it takes to change the clock period, and the
period of each correction. Since the corrections require four periods of the low-frequency base clock
(4*
τIBASE), and since ICLK is N (the ICG multiply factor for the desired frequency) times faster than
IBASE, each correction takes 4*N*
τICLK. The period of ICLK, however, will vary as the corrections occur.
6.4.6.1 Settling to Within 15%
When the error is greater than 15%, the filter takes eight corrections to double or halve the clock period.
Due to how the DCO increases or decreases the clock period, the total period of these eight corrections
is approximately 11 times the period of the fastest correction. (If the corrections were perfectly linear, the
total period would be 11.5 times the minimum period; however, the ring must be slightly non-linear.)
Therefore, the total time it takes to double or halve the clock period is 44*N*tICLKFAST.
If the clock period needs more than doubled or halved, the same relationship applies, only for each time
the clock period needs doubled, the total number of cycles doubles.
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