參數(shù)資料
型號(hào)： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 140/158頁
文件大小： 1020K
代理商： MC68HC908RK2DW
Internal Clock Generator Module (ICG)
MC68HC908RK2 Data Sheet, Rev. 5.1
82
Freescale Semiconductor
6.7.4 ICG DCO Divider Register
DDIV3–DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
Incrementing DDIV will add another divide-by-two, doubling the period (halving the frequency).
Decrementing has the opposite effect. DDIV cannot be written when ICGON is set to prevent
inadvertent frequency shifting. When ICGON is set, DDIV is controlled by the digital loop filter. The
range of valid values for DDIV is from $0 to $9. Values of $A–$F are interpreted the same as $9. Since
the DCO is active during reset, reset has no effect on DSTG and the value may vary.
6.7.5 ICG DCO Stage Register
DSTG7–DSTG0 — ICG DCO Stage Control Bits
These bits indicate the number of stages DSTG (above the minimum) in the digitally controlled
oscillator. The total number of stages is approximately equal to $1FF, so changing DSTG from $00 to
$FF will approximately double the period. Incrementing DSTG will increase the period (decrease the
frequency) by 0.202% to 0.368% (decrementing has the opposite effect). DSTG cannot be written
when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is controlled
by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG and the
value may vary.
Address: $0039
Bit 7
654321
Bit 0
Read:
RRRR
DDIV3
DDIV2
DDIV1
DDIV0
Write:
Reset:
0000
UUUU
R
= Reserved
U = Unaffected
Figure 6-15. ICG DCO Divider Register (ICGDVR)
Address: $003A
Bit 7
654321
Bit 0
Read:
DSTG7
DSTG6
DSTG5
DSTG4
DSTG3
DSTG2
DSTG1
DSTG0
Write:
Reset:
Unaffected by reset
Figure 6-16. ICG DCO Stage Register (ICGDSR)
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