參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 27/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Timer Interface Module (TIM)
MC68HC908RK2 Data Sheet, Rev. 5.1
122
Freescale Semiconductor
11.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, TCLK. The
prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIM status and control register select the TIM clock source.
11.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH and TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
11.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
$0024
Timer Counter Modulo
Register Low (TMODL)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
11111111
$0025
Timer Channel 0 Status and
Control Register (TSC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
00000000
$0026
Timer Channel 0 Register
High (TCH0H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0027
Timer Channel 0 Register
Low (TCH0L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
$0028
Timer Channel 1 Status and
Control Register (TSC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
$0029
Timer Channel 1 Register
High (TCH1H))
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$002A
Timer Channel 1 Register
Low (TCH1L))
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
Figure 11-3. TIM I/O Register Summary (Continued)
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