參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 44/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Development Support
MC68HC908RK2 Data Sheet, Rev. 5.1
138
Freescale Semiconductor
12.2.3.2 Break Address Registers
The break address registers contain the high and low bytes of the desired breakpoint address. Reset
clears the break address registers.
12.3 Monitor Module
This subsection describes the monitor read-only memory (MON). The MON allows complete testing of the
MCU through a single-wire interface with a host computer.
Features include:
Normal user-mode pin functionality
One pin dedicated to serial communication between monitor ROM and host computer
Standard mark/space non-return-to-zero (NRZ) communication with host computer
9600 baud communication with host computer when using a 9.8304-MHz crystal
Execution of code in random-access memory (RAM) or FLASH
FLASH security
FLASH programming
12.3.1 Functional Description
Monitor ROM receives and executes commands from a host computer. Figure 12-5 shows a sample
circuit used to enter monitor mode and communicate with a host computer via a standard RS-232
interface.
While simple monitor commands can access any memory address, the MC68HC908RK2 has a FLASH
security feature to prevent external viewing of the contents of FLASH. Proper procedures must be
followed to verify FLASH content. Access to the FLASH is denied to unauthorized users of
customer-specified software (see 12.3.2 Security).
In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0
retain normal operating mode functions. All communication between the host computer and the MCU is
through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host
computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor.
Register Name and Address: BRKH—$FE0C
Bit 7
654321
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
00000000
Register Name and Address: BRKL—$FE0D
Read:
Bit 7
654321
Bit 0
Write:
Reset:
00000000
Figure 12-4. Break Address Registers (BRKH and BRKL)
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