參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 87/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Memory
MC68HC908RK2 Data Sheet, Rev. 5.1
34
Freescale Semiconductor
2.5.5 FLASH 2TS Block Protection
NOTE
In performing a program or erase operation, the FLASH 2TS block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
Due to the ability of the on-board charge pump to erase and program the FLASH 2TS memory in the target
application, provision is made for protecting blocks of memory from unintentional erase or program
operations due to system malfunction. This protection is implemented by a reserved location in the
memory for block protect information. This block protect register must be read before setting HVEN = 1.
When the block protect register is read, its contents are latched by the FLASH 2TS control logic. If the
address range for an erase or program operation includes a protected block, the PGM or ERASE bit is
cleared which prevents the HVEN bit in the FLASH 2TS control register from being set such that no
high-voltage operation is allowed in the array.
When the block protect register is erased (all 0s), the entire memory is accessible for program and erase.
When bits within the register are programmed, they lock blocks of memory address ranges as shown in
2.5.6 FLASH 2TS Block Protect Register. The block protect register itself can be erased or programmed
only with an external voltage VTST present on the IRQ pin. The presence of VTST on the IRQ pin also
allows entry into monitor mode out of reset. Therefore, the ability to change the block protect register is
voltage-level dependent and can occur in either user or monitor modes.
2.5.6 FLASH 2TS Block Protect Register
The block protect register (FLBPR) is implemented as a byte within the FLASH 2TS memory. Each bit,
when programmed, protects a range of addresses in the FLASH 2TS.
BPR3 — Block Protect Register Bit 3
This bit protects the memory contents in the address ranges $7A00–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block Protect Register Bit 2
This bit protects the memory contents in the address ranges $7900–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block Protect Register Bit 1
This bit protects the memory contents in the address ranges $7880–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
Address:
$FFF0
Bit 7
654321
Bit 0
Read:
RRRR
BPR3
BPR2
BPR1
BPR0
Write:
Reset:
Unaffected by reset
R= Reserved
Figure 2-5. FLASH 2TS Block Protect Register (FLBPR)
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