參數(shù)資料
型號: MC68HC908RK2DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 11/158頁
文件大?。?/td> 1020K
代理商: MC68HC908RK2DW
System Integration Module (SIM)
MC68HC908RK2 Data Sheet, Rev. 5.1
108
Freescale Semiconductor
Figure 10-7. POR Recovery
10.3.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR) if the COPD bit in the CONFIG register is at 0. See Chapter 4 Computer Operating
10.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the configuration register (CONFIG) is 0, the SIM treats the STOP
instruction as an illegal opcode and causes an illegal opcode reset.
10.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset.
10.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the VLVR
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG register are at 0. The RST pin will be held low until the SIM
counts 4096 CGMXCLK cycles after VDD rises above VLVR+ HLVR. Another 64 CGMXCLK cycles later,
the CPU is released from reset to allow the reset vector sequence to occur. See Chapter 8 Low-Voltage
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE
$FFFF
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