參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 127/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Internal Clock Generator Module (ICG)
MC68HC908RK2 Data Sheet, Rev. 5.1
70
Freescale Semiconductor
Figure 6-8. Code Example for Switching Clock Sources
6.4.2 Enabling the Clock Monitor
Many applications require the clock monitor to determine if one of the clock sources has become inactive,
so the other can be used to recover from a potentially dangerous situation. Using the clock monitor
requires both clocks to be active (ECGON and ICGON both set). To enable the clock monitor, both clocks
also must be stable (ECGS and ICGS both set). This is to prevent the use of the clock monitor when a
clock is first turned on and potentially unstable.
Enabling the clock monitor and clock monitor interrupts requires a flow similar to this flow:
1.
Enable the alternate clock source
2.
Wait for both clock sources to be stable
3.
Switch to the desired clock source if necessary
4.
Enable the clock monitor
5.
Enable clock monitor interrupts
These events must happen in sequence. A short assembly code example of how to employ this flow is
shown in Figure 6-9. This code is for illustrative purposes only and does not represent valid syntax for any
particular assembler.
Figure 6-9. Code Example for Enabling the Clock Monitor
;Clock Switching Code Example
;This code switches from Internal to External clock
;Clock Monitor and interrupts are not enabled
start
lda
#$13
;Mask for CS, ECGON, ECGS
;If switching from External to Internal, mask is $0C.
loop
**
;Other code here, such as writing the COP, since ECGS may
;take some time to set
sta
icgcr
;Try to set CS, ECGON and clear ICGON. ICGON will not
;clear until CS is set, and CS will not set until
;ECGON and ECGS are set.
cmpa
icgcr
;Check to see if ECGS set, then CS set, then ICGON clear
;Clock Monitor Enabling Code Example
;This code turns on both clocks, selects the desired
; one, then turns on the Clock Monitor and Interrupts
start
lda
#$AF
;Mask for CMIE, CMON, ICGON, ICGS, ECGON, ECGS
; If Internal Clock desired, mask is $AF
; If External Clock desired, mask is $BF
; If interrupts not desired mask is $2F int; $3F ext
loop
**
;Other code here, such as writing the COP, since ECGS
; and ICGS may take some time to set.
sta
icgcr
;Try to set CMIE. CMIE wont set until CMON set; CMON
; won’t set until ICGON, ICGS, ECGON, ECGS set.
brset
6,ICGCR,error
;Verify CMF is not set
cmpa
icgcr
;Check if ECGS set, then CMON set, then CMIE set
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