參數資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數： 131/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Internal Clock Generator Module (ICG)
MC68HC908RK2 Data Sheet, Rev. 5.1
74
Freescale Semiconductor
That is, when transitioning from fast to slow:
Going from the initial speed to half speed takes 44*N*tICLKFAST
From half speed to quarter speed takes 88*N*tICLKFAST
Going from quarter speed to eighth speed takes 176*N*tICLKFAST, and so on.
This series can be expressed as (2x–1)*44*N*tICLKFAST, where x is the number of times the speed needs
doubled or halved. Since 2x happens to be equal to
τICLKSLOW/τICLKFAST, the equation reduces to
44*N*(
τICLKSLOW-τICLKFAST). Note that increasing speed takes much longer than decreasing speed since
N is higher. This can be expressed in terms of the initial clock period (
τ1) minus the final clock period (τ2)
as such:
6.4.6.2 Settling to Within 5%
Once the clock period is within 15% of the desired clock period, the filter starts making smaller
adjustments. When between 15% and 5% error, each correction will adjust the clock period between
1.61% and 2.94%. In this mode, a maximum of eight corrections will be required to get to less than 5%
error. Since the clock period is relatively close to desired, each correction takes approximately the same
period of time, or 4*
τIBASE. At this point, the internal clock stable bit (ICGS) will be set and the clock
frequency is usable, although the error will be as high as 5%. The total time to this point is:
6.4.6.3 Total Settling Time
Once the clock period is within 5% of the desired clock period, the filter starts making minimum
adjustments. In this mode, each correction will adjust the frequency between 0.202% and 0.368%. A
maximum of 24 corrections will be required to get to the minimum error. Each correction takes
approximately the same period of time or 4*
τIBASE. Added to the corrections for 15% to 5%, this makes
32 corrections (128*
τIBASE) to get from 15% to the minimum error. The total time to the minimum error is:
The equations for
τ15, τ5, and τtot are dependent on the actual initial and final clock periods τ1 and τ2, not
the nominal. This means the variability in the ICLK frequency due to process, temperature, and voltage
must be considered. Additionally, other process factors and noise can affect the actual tolerances of the
points at which the filter changes modes. This means a worst case adjustment of up to 35% (ICLK clock
period tolerance plus 10%) must be added. This adjustment can be reduced with trimming. Table 6-4
shows some typical values for settling time.
Table 6-4. Typical Settling Time Examples
τ1
τ2
N
τ15
τ5
τtot
1/ (6.45 MHz)
1/ (25.8 MHz)
84
430
s
535
s
850
s
1/ (25.8 MHz)
1/ (6.45 MHz)
21
107
s
212
s
525
s
1/ (25.8 MHz)
1/ (307.2 kHz)
1
141
s
246
s
560
s
1/ (307.2 kHz)
1/ (25.8 MHz)
84
11.9 ms
12.0 ms
12.3 ms
τ
15
abs 44N
τ
1
τ
2
–
()
[]
=
τ
5
abs 44N
τ
1
τ
2
–
()
[] 32τ
IBASE
+
=
τ
tot
abs 44N
τ
1
τ
2
–
()
[] 128τ
IBASE
+
=
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