參數(shù)資料
型號(hào)： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 157/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Input/Output (I/O) Ports
MC68HC908RK2 Data Sheet, Rev. 5.1
98
Freescale Semiconductor
9.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight port A pins.
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBD[6:1] — Keyboard Wakeup Pins
The keyboard interrupt enable bits, KBIE[6:1], in the keyboard interrupt control register enable the port
A pin as external interrupt pins and related internal pullup resistor. See Chapter 7 Keyboard/External
NOTE
The enabling of a keyboard interrupt pin will overide the corresponding
definition of the pin in the data direction register. However, the data
direction register bit must be a 0 for software to read the pin.
9.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Address:
$0000
Bit 7
654321
Bit 0
Read:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Write:
Reset:
Unaffected by reset
Alternate
Function:
KBD6
KBD5
KBD4
KBD3
KBD2
KBD1
= Unimplemented
Figure 9-2. Port A Data Register (PTA)
Address:
$0004
Bit 7
654321
Bit 0
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
Figure 9-3. Data Direction Register A (DDRA)
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