參數(shù)資料
型號： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 139/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
I/O Registers
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
81
ECGS — External Clock Generator Stable Bit
This read-only bit indicates when at least 4096 external clock (ECLK) cycles have elapsed since the
external clock generator was enabled. This is not an assurance of the stability of ECLK but is meant
to provide a start-up delay. This bit is forced clear when the clock monitor determines ECLK is inactive,
when ECGON is clear, or during reset.
1 = 4096 ECLK cycles have elapsed since ECGON was set.
0 = External cock is unstable, inactive, or disabled.
6.7.2 ICG Multiplier Register
N6–N0 — ICG Multiplier Factor Bits
These read/write bits change the multiplier used by the internal clock generator. The internal clock
(ICLK) will be (307.2 kHz
±25%) * N. A value of $00 in this register is interpreted the same as a value
of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal
21) for default frequency of 6.45 MHz
±25% (1.613 MHz ±25% bus).
6.7.3 ICG Trim Register
TRIM7–TRIM0 — ICG Trim Factor Bits
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved to
±2%. Incrementing this register by one decreases
the frequency by 0.195 percent of the unadjusted value. Decrementing this register by one increases
the frequency by 0.195%. This register cannot be written when the CMON bit is set. Reset sets these
bits to $80, centering the range of possible adjustment.
NOTE
It is recommended that the user preserve a copy of the contents of the ICG
trim register (ICGTR) in non-volitale memory.
Address $7FEF is reserved for an optional factory-determined ICG trim
value. Consult with a local Freescale representative for more information
and availability of this option.
Address: $0037
Bit 7
654321
Bit 0
Read:
R
N6N5
N4N3N2
N1
N0
Write:
Reset:
00010101
R
= Reserved
Figure 6-13. ICG Multiplier Register (ICGMR)
Address: $0038
Bit 7
654321
Bit 0
Read:
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
Write:
Reset:
10000000
Figure 6-14. ICG Trim Register (ICGTR)
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